1. Field of the Invention
The present invention relates to the field of display technology, and in particular to a method for manufacturing a low-temperature polycrystalline silicon (LTPS) thin-film-transistor (TFT) substrate and a LTPS TFT substrate.
2. The Related Arts
The development of flat-panel displays brings successive demands for high-definition and low-power-consumption panels. Low-temperature polycrystalline silicon (LTPS), which has a relatively high mobility, has gained much attention from the industry of liquid crystal displays (LCDs) and organic light emitting diodes (OLEDs) and is considered an important material for achieving low-cost full-color flat-panel displays. For a flat-panel display, adopting a material of LTPS may possess various advantages including high definition, fast response speed, high brightness, high aperture rate, and low power consumption. In addition, LTPS can be used in manufacture in a low temperature and is applicable to the manufacture of C-MOS circuits, making it widely used to meet the needs of high definition and low power consumption for panels.
LTPS is a branch of the polycrystalline silicon (poly-Si) technology. The molecular structure of polycrystalline silicon shows an ordered and directional arrangement in a crystal grain. As such, the mobility thereof is faster than that of amorphous silicon (a-Si) that is generally randomly arranged by 200-300 times, making it possible to significantly increase the response speed of a flat-panel display. Various crystallization processes are available for manufacturing LTPS, among which primary ones are chemical vapor deposition (CVD), solid phase crystallization (SPC), metal-induced crystallization (MIC), metal-induced lateral crystallization (MILC), and excimer laser annealing (ELA).
Referring to FIGS. 1-6, a known method for manufacturing a LTPS TFT substrate generally comprises the following steps: Step 1: providing a substrate 100 and depositing a buffer layer 200 on the glass substrate 100; Step 2: depositing an amorphous silicon (a-Si) layer 300 on the buffer layer 200; Step 3: applying ion implantation to implant a predetermined dosage of boron into the amorphous silicon layer 300 and then applying rapid thermal anneal (RTA) to heat for 20-30 minutes to have the amorphous silicon crystallized into polycrystalline silicon (poly-Si), and then etching and removing an electrically conductive layer that precipitates on a surface of the polycrystalline silicon during the crystallization process and has a low electrical resistance with only a desired polycrystalline silicon layer 400 left; Step 4: patterning the polycrystalline silicon layer 400 through photolithographic and etching operations to form a polycrystalline silicon semiconductor layer 450; Step 5: coating photoresist on the polycrystalline silicon semiconductor layer 450 and conducting exposure and development on the photoresist to form a photoresist layer 550 on the polycrystalline silicon semiconductor layer 450 in such a way that two end portions of the polycrystalline silicon semiconductor layer 450 are exposed; implanting boron ions into the two end portions of the polycrystalline silicon semiconductor layer 450 through ion implantation with the photoresist layer 550 serving as a shielding layer so as to form source/drain contact zones 451; Step 6: peeling off the photoresist layer 550 and forming, in sequence, a gate insulation layer 500, a gate terminal 600, an interlayer insulation layer 700, and source/drain terminals 800 on the polycrystalline silicon semiconductor layer 450.
In the above-described method for manufacturing a LTPS TFT substrate, the formation of low-temperature polycrystalline silicon is achieved with a conventional SPC crystallization process. Such a SPC crystallization process, although forming grain sizes showing excellent consistency, the grain sizes are small and the grain boundaries are numerous, imposing influences on the mobility of charge carriers and the leakage current of a TFT device.